Increasing demands for high quality test have been driven by ever-expanding reliability needs combined with the ability to handle more complex and diverse designs. As circuits grow in size, it becomes increasingly expensive to maintain high level of test coverage. This is due to prohibitively large volumes of test data and long test application times. A method employed to reduce the amount of test data is, therefore, instrumental in maintaining the overall high efficiency of a testing scheme. On-chip test compression has already established itself as a mainstream DFT (design for test) methodology with a direct bearing on the manufacturing test cost.
A majority of existing test compression schemes, including the LFSR (linear feedback shift register) coding, take advantage of low test cube fill rates. They treat external test data as Boolean variables and create linear expressions filling conceptually all scan cells. Test patterns are then delivered, in a compressed and encoded form, through tester channels to an on-chip LFSR (decoder). The LFSR expands the compressed test patterns into the actual data and loads them into internal scan chains. The LFSR coding was refined under the name of static LFSR reseeding in a number of approaches. In principle, the static LFSR reseeding computes a seed for each test cube. The encoding capability of these methods is limited by the LFSR size, unless a group of scan slices is encoded per seed. Another drawback is that the loading of the seed and loading/unloading of the scan chains are done in two non-overlapping phases, resulting in inefficient utilization of the tester. This can be alleviated by employing additional shadow registers. One can also modify patterns produced by the LFSR to increase test coverage while reducing the number of seeds. Finally, as the number of specified bits may vary in successive test cubes, variable-length seeds were deployed to improve the encoding efficiency of the conventional static reseeding schemes.
The dynamic LFSR reseeding stands in vivid contrast to its static counterpart. It continuously injects free variables into a decompressor as it loads the scan chains. This shift in compression paradigm, as proposed for the embedded deterministic test (EDT), reduces test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. Such a scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology with a very simple flow. Reduction of both tester scan buffer data volume and scan test time is also accomplished in the schemes based on the On-Product MISR, where a bandwidth overhead for external test response compaction is reduced by on-chip signature generation while still supplying test stimuli from ATE.
Both test application time and test data volume can be reduced by broadcasting the same test vector to several scan chains through a single input. To apply this technique, a given test pattern must not contain contradictory values on corresponding cells in different chains loaded through the same input. This can be guaranteed by incorporating the compression-imposed constraints during test generation, e.g., by tying dependent inputs together in the circuit description provided to ATPG.
Other forms of compression are based on XOR networks, hybrid patterns, folding counters, bit flipping, non-linear de-compressors, reconfigurable networks, and reuse of scan chains. A Star-BIST reduces the amount of data by using clusters of correlated test patterns. A test generator stores a small number of vectors which serve as centers of clusters, and it applies each center test vector multiple times. Every time the center vector is shifted into the circuit, some of its positions are randomly or deterministically complemented. A separate group of techniques uses various forms of compression based on run-length, statistical, constructive, and Golomb codes. Though usable on any set of test cubes, the code-based methods are less than efficient at exploiting test cube low fill rates
Test compression schemes are typically characterized by their encoding efficiency, i.e., a ratio of successfully encoded specified bits to the total number of deployed data bits. In particular, the encoding efficiency of plain reseeding-based schemes can reach, at their best, the value of 1.00. The encoding efficiency can be increased either by repeating certain patterns at the rates, which are adjusted to the requirements of test cubes, or by embedding certain bits into LFSR-generated sequences. The latter technique requires additional memory to store compressed information necessary to handle separately test cubes that otherwise would require excessively large LFSRs to be encoded.
Further increase in the encoding efficiency is possible due to regularities occurring in test patterns. Dictionary-based approaches exploit the fact that certain vector values within test patterns are likely to be repeated. When they do occur, they may be encoded as pointers to on-chip memory locations storing vectors reused during test. The similar concept is used in packet-based encoding and nine-coded compression. The recently proposed restrict encoding combines LFSR reseeding with a pre-computed dictionary of test vector values which are injected at the same positions over multiple test patterns. The approach requires, however, solving the clique covering and traveling salesman problems.